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USBLC6-2
Very low capacitance ESD protection
Features

2 data lines protection Protects VBUS Very low capacitance: 3.5 pF max. Very low leakage current: 150 nA max. SOT-666 and SOT23-6L packages RoHS compliant
SOT23-6L USBLC6-2SC6
SOT-666 USBLC6-2P6
Benefits

Applications

Very low capacitance between lines to GND for optimized data integrity and speed Low PCB space consumption: 2.9 mm2 max for SOT-666 and 9mm max for SOT23-6L Enhanced ESD protection. IEC 61000-4-2 level 4 compliance guaranteed at device level, hence greater immunity at system level ESD protection of VBUS High reliability offered by monolithic integration Low leakage current for longer operation of battery powered devices Fast response time Consistent D+ / D- signal balance: - Very low capacitance matching tolerance I/O to GND = 0.015 pF - Compliant with USB 2.0 requirements
USB 2.0 ports up to 480 Mb/s (high speed) Compatible with USB 1.1 low and full speed Ethernet port: 10/100 Mb/s SIM card protection Video line protection Portable electronics
Description
The USBLC6-2SC6 and USBLC6-2P6 are monolithic application specific devices dedicated to ESD protection of high speed interfaces, such as USB 2.0, Ethernet links and video lines. The very low line capacitance secures a high level of signal integrity without compromising in protecting sensitive chips against the most stringent characterized ESD strikes. Figure 1. Functional diagram
I/O1
1
Complies with the following standards
IEC 61000-4-2 level 4: - 15 kV (air discharge) - 8 kV (contact discharge)
6
I/O1
GND
2
5
VBUS
I/O2
3
4
I/O2
March 2008
Rev 3
1/14
www.st.com 14
Characteristics
USBLC6-2
1
Characteristics
Table 1.
Symbol
Absolute ratings
Parameter IEC 61000-4-2 air discharge IEC 61000-4-2 contact discharge MIL STD883G-Method 3015-7 Value 15 15 25 -55 to +150 -40 to +125 260 Unit
VPP Tstg Tj TL
Peak pulse voltage Storage temperature range
kV C C C
Operating junction temperature range Lead solder temperature (10 seconds duration)
Table 2.
Symbol VRM IRM VBR VF
Electrical characteristics (Tamb = 25 C)
Value Parameter Reverse stand-off voltage Leakage current Breakdown voltage between VBUS and GND Forward voltage VRM = 5 V IR = 1 mA IF = 10 mA IPP = 1 A, 8/20 s Any I/O pin to GND 6 1.1 12 17 2.5 0.015 Capacitance between I/O VR = 1.65 V 1.2 0.04 1.7 pF 3.5 pF 10 Test conditions Min. Typ. Max. 5 150 V nA V V V V Unit
VCL
Clamping voltage IPP = 5 A, 8/20 s Any I/O pin to GND Capacitance between I/O and GND VR = 1.65 V
Ci/o-GND Ci/o-GND Ci/o-i/o Ci/o-i/o
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USBLC6-2
Characteristics
Figure 2.
C(pF)
3.0
Capacitance versus voltage (typical values)
Figure 3.
C(pF)
2.8 2.6
Line capacitance versus frequency (typical values)
CO=I/O-GND
2.5
F=1MHz VOSC=30mVRMS Tj=25C
2.4 2.2 2.0 1.8 1.6 1.4
VOSC=30mVRMS Tj=25C VLINE=0V to 3.3V
2.0
1.5
Cj=I/O-I/O
1.2 1.0 0.8 0.6
1.0
0.5
0.4
Data line voltage (V)
0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.2 0.0 1 10
F(MHz)
100 1000
Figure 4.
Relative variation of leakage current versus junction temperature (typical values)
Figure 5.
Frequency response
IRM[Tj] / IRM[Tj=25C]
100
VBUS=5V
0.00 S21(dB) -5.00
-10.00
10
-15.00
Tj(C)
1 25 50 75 100 125
-20.00 100.0k 1.0M
F(Hz)
10.0M 100.0M 1.0G
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Technical information
USBLC6-2
2
2.1
Technical information
Surge protection
The USBLC6-2 is particularly optimized to perform surge protection based on the rail to rail topology. The clamping voltage VCL can be calculated as follow : VCL+ = VTRANSIL + VF for positive surges VCL- = - VF for negative surges with: VF = VT + Rd.Ip (VF forward drop voltage) / (VT forward drop threshold voltage) and VTRANSIL = VBR + Rd_TRANSIL.IP Calculation example We assume that the value of the dynamic resistance of the clamping diode is typically: Rd = 0.5 and VT = 1.1 V We assume that the value of the dynamic resistance of the transil diode is typically: Rd_TRANSIL = 0.5 and VBR = 6.1 V For an IEC 61000-4-2 surge Level 4 (Contact Discharge: Vg = 8 kV, Rg = 330 ), VBUS = +5 V, and if in first approximation, we assume that : Ip = Vg / Rg = 24 A. So, we find: VCL+ = +31.2 V VCL- = -13 V
Note:
The calculations do not take into account phenomena due to parasitic inductances.
2.2
Surge protection application example
If we consider that the connections from the pin VBUS to VCC, from I/O to data line and from GND to PCB GND plane are done by tracks of 10 mm long and 0.5 mm large, we assume that the parasitic inductances LVBUS, LI/O and LGND of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs on data line, due to the rise time of this spike (tr=1ns), the voltage VCL has an extra value equal to LI/O.dl/dt+LGND.dI/dt. The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns The overvoltage due to the parasitic inductances is: LI/O.dl/dt = LGND.dI/dt = 6 nH x 24 A/ns = 144 V By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be : VCL+ = +31.2 + 144 + 144 = 319.2 V VCL- = -13.1 - 144 - 144 = -301.1 V
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USBLC6-2
Technical information We can significantly reduce this phenomena with simple layout optimization. It is for this reason that some recommendations have to be followed (see 2.3: How to ensure good ESD protection). Figure 6. ESD behavior: parasitic phenomena due to unsuitable layout
ESD surge on data line VBUS Data line
LI/O LI/O di dt LVBUS VCC pin VF VTRANSIL I/O pin VCL VTRANSIL + VF t tr = 1 ns GND pin tr = 1 ns LGND LGND di dt - VF t LI/O di + LGND di dt dt VCL+
Positive Surge
VCL+ = VTRANSIL + VF + LI/O di + LGND di dt dt VCL- = -VF - LI/O di - LGND di dt dt V TRANSIL = VBR + Rd.Ip
surge > 0 surge > 0
-LI/O di - LGND di dt dt
Negative Surge
VCL-
2.3
How to ensure good ESD protection
While the USBLC6-2 provides high immunity to ESD surge, efficient protection depends on the layout of the board. In the same way, with the rail to rail topology, the track from data lines to I/O pins, from VCC to VBUS pin and from GND plane to GND pin must be as short as possible to avoid overvoltages due to parasitic phenomena (see Figure 6. and Figure 7. for layout consideration)
Figure 7.
ESD behavior: layout optimization
Figure 8.
ESD behavior: measurement conditions
1 1
6
ESD SURGE
2 5
3
4
TEST BOARD IN OUT
USBLC6-2SC6
Unsuitable layout
1 1 6
+5 V
2
5
3
4
Optimized layout
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Technical information
USBLC6-2
Figure 9.
ESD response to IEC 61000-4-2 (+15 kV air discharge)
Figure 10. ESD response to IEC 61000-4-2 (-15 kV air discharge)
Vin
Vin
Vout
Vout
Important:
A good precaution to take is to put the protection device as close as possible to the disturbance source (generally the connector).
2.4
2.4.1
Crosstalk behavior
Crosstalk phenomenon
Figure 11. Crosstalk phenomenon
RG1 Line 1 1 VG1 + 12VG2
VG1 RG2 Line 2
RL1
VG2
RL2
2VG2 + 21VG1
DRIVERS
RECEIVERS
The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (12 or 21) increases when the gap across lines decreases, particularly in silicon dice. In the above example the expected signal on load RL2 is 2VG2, in fact the real voltage at this point has got an extra value 21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few k).
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USBLC6-2 Figure 12. Analog crosstalk measurements
Technical information
TEST BOARD NETWORK ANALYSER PORT 1
USBLC6-2SC6
NETWORK ANALYSER PORT 2 Vbus
Figure 12. shows the measurement circuit for the analog application. In usual frequency range of analog signals (up to 240 MHz) the effect on disturbed line is less than -55 db ( see Figure 13.). Figure 13. Analog crosstalk results
dB
0.00
- 30.00
- 60.00
- 90.00
F (Hz)
- 120.00 100.0k 1.0M 10.0M 100.0M 1.0G
As the USBLC6-2 is designed to protect high speed data lines, it must ensure a good transmission of operating signals. The frequency response (Figure 5.) gives attenuation information and shows that the USBLC6-2 is well suitable for data line transmission up to 480 Mbit/s while it works as a filter for undesirable signals like GSM (900 MHz) frequencies, for instance.
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Technical information
USBLC6-2
2.5
Application examples
Figure 14. USB 2.0 port application diagram using USBLC6-2
+ 3.3V DEVICEUPSTREAM RPU TRANSCEIVER
SW2
VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS GND TX LS/FS + TX LS/FS -
+ 5V
USB connector
Protecting Bus Switch
HUBDOWNSTREAM TRANSCEIVER
SW1
VBUS D+
DRS RS
VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS -
GND
RS RS RPD RPD
GND TX LS/FS + TX LS/FS -
USBLC6-2SC6
+ 3.3V DEVICEUPSTREAM RPU TRANSCEIVER
SW2
VBUS RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS GND TX LS/FS + TX LS/FS -
SW1
USB connector
VBUS D+
DRS RS
RX LS/FS + RX HS + TX HS + RX LS/FS RX HS TX HS -
GND
RS
USBLC6-4SC6
GND TX LS/FS +
USBLC6-2P6
RS RPD RPD
TX LS/FS -
Mode Low Speed LS Full Speed FS High Speed HS
SW1 Open Closed
SW2 Closed Open
Closed then open Open
Figure 15. T1/E1/Ethernet protection
+VCC
USBLC6-2SC6
Tx
SMP75-8
100nF
DATA TRANSCEIVER
+VCC
USBLC6-2SC6
Rx
SMP75-8
100nF
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USBLC6-2
Technical information
2.6
PSpice model
Figure 16. shows the PSpice model of one USBLC6-2 cell. In this model, the diodes are defined by the PSpice parameters given in Figure 17.
Figure 16. PSpice model
LI/O D+in
RI/O MODEL = Dlow MODEL = Dhigh
RI/O
LI/O D+out
LGND GND
RGND
MODEL = Dzener
RI/O
LI/O VBUS
MODEL = Dlow LI/O D-in RI/O
MODEL = Dhigh RI/O LI/O D-out
Note:
This simulation model is available only for an ambient temperature of 27 C. Figure 18. USBLC6-2 PCB layout considerations
Figure 17. PSpice parameters
Dlow BV CJ0 IBV M RS VJ TT 50 0.9p 1m 0.3333 0.2 0.6 0.1u
Dhigh 50 2.0p 1m 0.3333 0.52 0.6 0.1u
Dzener 7.3 40p 1m 0.3333 0.84 0.6 0.1u
LI/O RI/O LGND RGND
750p 110m 550p 60m
GND D-in D-out
VBUS
D+in
1
D+out
CBUS = 100nF
USBLC6-2
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Ordering information scheme
USBLC6-2
3
Ordering information scheme
Figure 19. Ordering information scheme
USB
Product Designation Low capacitance Breakdown Voltage 6 = 6 Volts Number of lines protected 2 = 2 lines Packages SC6 = SOT23-6L P6 = SOT-666
LC
6-2
xxx
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USBLC6-2
Package information
4
Package information
Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Table 3. SOT-666 dimensions
b1 L1
Dimensions Ref. Millimeters Min. Typ. Max. Min. Inches Typ. Max. 0.024 0.007 0.013
L3 b D E1
A A3 b b1
A L2 E A3
0.45 0.08 0.17 0.19 1.50 1.50 1.10 0.50 0.19 0.10 0.10 0.27
0.60 0.018 0.18 0.003 0.34 0.007
0.34 0.007 0.011 0.013 1.70 0.059 1.70 0.059 1.30 0.043 0.020 0.007 0.30 0.004 0.004 0.012 0.067 0.067 0.051
D E E1 e L1 L2
e
L3
Figure 20. SOT-666 footprint
0.50
Figure 21. SOT-666 marking
e3
0.62 2.60
xxx z y ww
e3: ECOPACK (Leadfree) XXX: Marking Z: Manufacturing location Y: Year WW: week
0.99
0.30
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Package information Table 4. SOT23-6L dimensions
Dimensions Ref.
A
E
USBLC6-2
Millimeters Min. Typ. Max. Min.
Inches Typ. Max. 0.057 0.004 0.051 0.020 0.008 0.118 0.069 0.037
A
e b e
D
0.90 0 0.90 0.35 0.09 2.80 1.50 0.95 2.60 0.10 0
1.45 0.035 0.10 0
A1 A2 b c
A2
1.30 0.035 0.50 0.014 0.20 0.004 3.05 0.11
D E
1.75 0.059
c
A1
e H L
L
H
3.00 0.102 0.60 0.004 10 0
0.118 0.024 10
Figure 22. SOT23-6L footprint
0.60
Figure 23. SOT23-6L marking
1.20
e3
3.50
2.30
0.95
1.10
xxx z y ww
e3: ECOPACK (Leadfree) XXX: Marking Z: Manufacturing location Y: Year WW: week
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USBLC6-2
Ordering information
5
Ordering information
Table 5. Ordering information
Marking UL26 F Package SOT23-6L SOT-666 Weight 16.7 mg 2.9 mg Base qty 3000 3000 Delivery mode Tape and reel Tape and reel
Ordering code USBLC6-2SC6 USBLC6-2P6
6
Revision history
Table 6.
Date 14-Mar-2005 07-Jun-2005
Document revision history
Revision 1 2 First issue. Format change to figure 3; no content changed. Added marking illustrations - Figures 21 and 23. Added ECOPACK statement. Updated operating junction temperature range in absolute ratings, page 2. Technical information section updated. Reformatted to current standards. Description of changes
20-Mar-2008
3
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USBLC6-2
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